This invention relates generally to data processing systems and more particularly to a computer system in which a number of units, including input/output (I/O) devices, one or more processors and a memory, communicate with one another over a common electrical bus.
Many contemporary computer system products have been designed to operate with a common electrical bus architecture in which all units connected with the bus send and receive messages, including address, data and control information, by means of a single set of signals. Such a system can be easily updated or enhanced as improved units, such as memory, I/O devices, processors and the like, become available, thereby increasing the useful life of the product. Such an enhancement can be made with a minor design effort involving an interface of the improved unit to the common bus. That is, the entire computer product, including hardware and software does not have to be redesigned to take advantage of improved performance characteristics of advanced memories, I/O devices, processors and the like.
In such common bus systems a unit generally obtains control of the bus by means of a bus request and bus grant procedure controlled by a bus control mechanism according to a prearranged priority scheme. Upon obtaining control, a unit is permitted to communicate with another unit by means of a set of fixed messages called bus commands. For example, an I/O device having data to be stored in the memory, upon obtaining use of the bus, sends a message directed to the memory consisting of the data, the address where it is to be stored and a memory write command. The memory upon sensing the command and, provided it is not busy with a prior request, captures the data and address information from the bus and performs the memory write operation. This memory write command is exemplary of a number of commands or messages which are unidirectional in nature and generally can be transmitted or completed in one transfer cycle of the bus such that the bus can thereafter be used by any of the system units for other communications.
Another group of commands or messages in such common bus systems are bidirectional in nature in that one unit sends a message (requesting message) to another unit requesting the other unit to answer back with a reply message at a later time. Exemplary of this type of message are memory read operations, call interrupt operations and the like. For example, in a memory read operation, an I/O device or a processor sends during a first bus transfer cycle a message consisting of a memory read command and a memory address. The memory interprets the command as a request for data to be read from memory at the received address and then returned to the sending unit. One way of handling this situation is to allow the sender to retain control of the bus until the memory has read and returned the data to the sender. This procedure is, however, unsatisfactory because a typical memory cycle is generally much longer than a bus transfer cycle such that the bus could be hung up (dedicated) with the memory read operation for a number of bus transfer cycles.
One solution to the hangup problem is to require the sender of the message to include therein its identity or bus address. This allows the memory to capture the memory address and the user's address, perform the required data read operation and return the data during a later bus transfer cycle to the original sender by using the saved sender address. The bus can therefore be free to handle other communications during the intervening time. Although this solution, which is exemplified in a system disclosed in U.S. Pat. No. 3,993,981 improves the system throughput, there is further room for improvement as the bulk of the communications on the common bus consist of messages requesting a reply and the corresponding reply messages.
In prior art arrangements, reply messages tend to be returned in the same time sequence in which the original requesting messages were transmitted. Such an arrangement is described in U.S. Pat. No. 4,015,246 in which the reply messages for read memory commands are returned over a set of data leads, separate and independent from another set which is devoted to original message traffic. This alleviates the original message bus hangup problem discussed above but does so at the expense of hanging up the reply bus (until the reply is transmitted). Moreover, the reply bus is dedicated to a single type of message traffic (memory to processor) and is therefore rather inflexible.